{"ID":3053246,"CreatedAt":"2026-06-04T04:41:36.695875263Z","UpdatedAt":"2026-06-05T21:13:48.551744587Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2606.04221","arxiv_id":"2606.04221","title":"Feasibility of Time-Domain DNN-Based Speech Enhancement on Embedded FPGA for Hearing Aid","abstract":"Hearing aids impose strict latency and power constraints that current DNN-based speech enhancement systems struggle to meet on embedded hardware. We characterize this gap by deploying both speech separation and denoising using the lightweight SuDoRM-RF++ architecture on the AMD-Xilinx Kria KV260, evaluated at FP32 and 16-bit fixed-point precision for each task. Across these configurations, first-sample latency tracks with on-chip parameter caching rather than arithmetic throughput, identifying data movement as the primary bottleneck. Precision reduction halves the model memory footprint without compromising objective speech quality. The fixed-point denoising accelerator achieves a first-sample latency of 9.7~ms, meeting the 10~ms clinical threshold, while speech separation reaches 16.0~ms. These measurements establish concrete resource requirements for embedded DNN-based speech enhancement and quantify the remaining gap to hearing aid deployment.","short_abstract":"Hearing aids impose strict latency and power constraints that current DNN-based speech enhancement systems struggle to meet on embedded hardware. We characterize this gap by deploying both speech separation and denoising using the lightweight SuDoRM-RF++ architecture on the AMD-Xilinx Kria KV260, evaluated at FP32 and...","url_abs":"https://arxiv.org/abs/2606.04221","url_pdf":"https://arxiv.org/pdf/2606.04221v1","authors":"[\"Feyisayo Olalere\",\"Umut Altin\",\"Kiki van der Heijden\",\"Marcel van Gerven\"]","published":"2026-06-02T21:17:00Z","proceeding":"cs.SD","tasks":"[\"cs.SD\",\"cs.AR\",\"eess.AS\"]","methods":"[]","has_code":false}