{"ID":2921140,"CreatedAt":"2026-06-02T02:42:49.606572591Z","UpdatedAt":"2026-06-04T06:21:04.369492701Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2606.01776","arxiv_id":"2606.01776","title":"A 32-Channel 3.53-μW Per Channel Brain-Machine Interface SoC Featuring Dual-Threshold Delta-modulation, In-Memory Spike Detection and Bi-SNN Based Motor Decoding","abstract":"With the scaling of sensor channel counts, systems confront challenges in frontend data sensing and on-implant data processing. This work presents a 32-channel fully event-based iBMI SoC in 65nm CMOS for an efficient neuromorphic signal processing pipeline. The SoC integrates a 32-channel dual-threshold delta modulation (DTDM) frontend array that provides up to 26x data compression at the frontend, an in-memory computing (IMC) spike detector (SPD) for efficient in-pixel spike detection, and a bipolar LIF-based spiking neural network (Bi-SNN) decoder for on-chip motor intention decoding (MID). Consuming only 3.53 μW per channel and achieving ~0.62 decoding R2 with a compact 0.034 mm2 per-channel area, the chip enables high-efficiency signal recording, processing, and decoding for implantable devices.","short_abstract":"With the scaling of sensor channel counts, systems confront challenges in frontend data sensing and on-implant data processing. This work presents a 32-channel fully event-based iBMI SoC in 65nm CMOS for an efficient neuromorphic signal processing pipeline. The SoC integrates a 32-channel dual-threshold delta modulatio...","url_abs":"https://arxiv.org/abs/2606.01776","url_pdf":"https://arxiv.org/pdf/2606.01776v1","authors":"[\"Ye Ke\",\"Zhengnan Fu\",\"Pao-Sheng Vincent Sun\",\"An Guo\",\"Shuai Dong\",\"Junyi Yang\",\"Yahan Yang\",\"Abdelrahman B. M. Eldaly\",\"Xin Si\",\"Leanne Chan\",\"Arindam Basu\"]","published":"2026-06-01T06:58:57Z","proceeding":"eess.SP","tasks":"[\"eess.SP\"]","methods":"[]","has_code":false}