{"ID":2898307,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2507.10561","arxiv_id":"2507.10561","title":"SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST","abstract":"Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.","short_abstract":"Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FP...","url_abs":"https://arxiv.org/abs/2507.10561","url_pdf":"https://arxiv.org/pdf/2507.10561v1","authors":"[\"Alessio Caviglia\",\"Filippo Marostica\",\"Alessio Carpegna\",\"Alessandro Savino\",\"Stefano Di Carlo\"]","published":"2025-07-04T08:22:13Z","proceeding":"cs.NE","tasks":"[\"cs.NE\",\"cs.CV\"]","methods":"[]","has_code":false}