{"ID":2896804,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2507.05556","arxiv_id":"2507.05556","title":"Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads","abstract":"Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PRAC performance estimation. We present the first real-machine performance analysis of PRAC. After verifying timing modifications on the latest CPUs using microbenchmarks, our analysis shows that PRAC's average and maximum overheads are just 1.06% and 3.28% for the SPEC CPU2017 workloads -- up to 9.15x lower than simulator-based reports. Further, we show that the close page policy minimizes this overhead by effectively hiding the elongated DRAM row precharge operations due to PRAC from the critical path.","short_abstract":"Per-Row Activation Counting (PRAC), a DRAM read disturbance mitigation method, modifies key DRAM timing parameters, reportedly causing significant performance overheads in simulator-based studies. However, given known discrepancies between simulators and real hardware, real-machine experiments are vital for accurate PR...","url_abs":"https://arxiv.org/abs/2507.05556","url_pdf":"https://arxiv.org/pdf/2507.05556v2","authors":"[\"Jumin Kim\",\"Seungmin Baek\",\"Minbok Wi\",\"Hwayong Nam\",\"Michael Jaemin Kim\",\"Sukhan Lee\",\"Kyomin Sohn\",\"Jung Ho Ahn\"]","published":"2025-07-08T00:38:44Z","proceeding":"cs.AR","tasks":"[\"cs.AR\",\"cs.CR\"]","methods":"[]","has_code":false}