{"ID":2894047,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2508.13159","arxiv_id":"2508.13159","title":"Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures","abstract":"Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structures account for an average of 6.34\\% (up to 12\\%) of the total nodes in the benchmark circuits. Experimental results demonstrate that our methods yields an average performance improvement of 8.8\\% (up to 22\\%) on simulating benchmark circuits which include a variety of functional modules such as ALUs, adders, multipliers, SEC/DED checkers, and interrupt controllers, with only 0.7\\% relative error.","short_abstract":"Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structur...","url_abs":"https://arxiv.org/abs/2508.13159","url_pdf":"https://arxiv.org/pdf/2508.13159v1","authors":"[\"Ruibai Tang\",\"Wenlai Zhao\"]","published":"2025-07-16T16:43:20Z","proceeding":"cs.AR","tasks":"[\"cs.AR\",\"cs.PF\"]","methods":"[]","has_code":false}