{"ID":2879086,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2508.16933","arxiv_id":"2508.16933","title":"TSPC-PFD: TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector","abstract":"Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of 4.41 uW at 3 GHz input frequency with a layout area of $10.42μm^2$.","short_abstract":"Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD design...","url_abs":"https://arxiv.org/abs/2508.16933","url_pdf":"https://arxiv.org/pdf/2508.16933v1","authors":"[\"Dhandeep Challagundla\",\"Venkata Krishna Vamsi Sundarapu\",\"Ignatius Bezzam\",\"Riadul Islam\"]","published":"2025-08-23T07:49:02Z","proceeding":"cs.ET","tasks":"[\"cs.ET\",\"eess.SP\"]","methods":"[]","has_code":false}