{"ID":2877003,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2508.20431","arxiv_id":"2508.20431","title":"Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS","abstract":"Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are reconstructed by reading out voltages from a 16-element electrode array and processing the data off-chip, and sources of variation in reconstruction are discussed. The EIT system presented in this work serves as a proof-of-concept towards using CMOS as a platform for co-integrated microfluidics and electronics.","short_abstract":"Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are r...","url_abs":"https://arxiv.org/abs/2508.20431","url_pdf":"https://arxiv.org/pdf/2508.20431v1","authors":"[\"Antonio Victor Machado de Oliveira\",\"Debjit Sarkar\",\"Ali Hajimiri\"]","published":"2025-08-28T05:05:34Z","proceeding":"physics.ins-det","tasks":"[\"physics.ins-det\",\"eess.SP\"]","methods":"[]","has_code":false}