{"ID":2871769,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2510.15902","arxiv_id":"2510.15902","title":"Fully Automated Verification Framework for Configurable IPs: From Requirements to Results","abstract":"The increasing competition in the semiconductor industry has created significant pressure to reduce chip prices while maintaining quality and reliability. Functional verification, particularly for configurable IPs, is a major contributor to development costs due to its complexity and resource-intensive nature. To address this, we propose a fully automated framework for requirements driven functional verification. The framework automates key processes, including vPlan generation, testbench creation, regression execution, and reporting in a requirements management tool, drastically reducing verification effort. This approach accelerates development cycles, minimizes human error, and enhances coverage, offering a scalable and efficient solution to the challenges of verifying configurable IPs.","short_abstract":"The increasing competition in the semiconductor industry has created significant pressure to reduce chip prices while maintaining quality and reliability. Functional verification, particularly for configurable IPs, is a major contributor to development costs due to its complexity and resource-intensive nature. To addre...","url_abs":"https://arxiv.org/abs/2510.15902","url_pdf":"https://arxiv.org/pdf/2510.15902v1","authors":"[\"Shuhang Zhang\",\"Jelena Radulovic\",\"Thorsten Dworzak\"]","published":"2025-09-12T11:42:09Z","proceeding":"cs.AR","tasks":"[\"cs.AR\",\"cs.ET\"]","methods":"[]","has_code":false}