{"ID":2866645,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2509.20215","arxiv_id":"2509.20215","title":"The Cream Rises to the Top: Efficient Reranking Method for Verilog Code Generation","abstract":"LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements and Verilog implementations, and propose VCD-RNK, a discriminator model tailored for efficient Verilog code reranking. Specifically, VCD-RNKincorporates Verilog-specific reasoning by distilling expert knowledge across three dimensions: code semantic analysis, test case generation, and functional correctness assessment. By explicitly simulating the above reasoning processes during inference, VCD-RNK effectively avoids computationally intensive test execution in existing methods.","short_abstract":"LLMs face significant challenges in Verilog generation due to limited domain-specific knowledge. While sampling techniques improve pass@k metrics, hardware engineers need one trustworthy solution rather than uncertain candidates. To bridge this gap, we formulate it as a semantic alignment problem between requirements a...","url_abs":"https://arxiv.org/abs/2509.20215","url_pdf":"https://arxiv.org/pdf/2509.20215v2","authors":"[\"Guang Yang\",\"Wei Zheng\",\"Xiang Chen\",\"Yifan Sun\",\"Fengji Zhang\",\"Terry Yue Zhuo\"]","published":"2025-09-24T15:12:21Z","proceeding":"cs.AR","tasks":"[\"cs.AR\",\"cs.AI\",\"cs.SE\"]","methods":"[\"Large Language Model\"]","has_code":false}