{"ID":2859215,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2510.21745","arxiv_id":"2510.21745","title":"Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis","abstract":"Excessive switching activity is a primary contributor to dynamic power dissipation in modern FPGAs, where fine-grained configurability amplifies signal toggling and associated capacitance. Conventional low-power techniques -- gating, clock-domain partitioning, and placement-aware netlist rewrites - either require intrusive design changes or offer diminishing returns as device densities grow. In this work, we present Simopt-power, a simulator-driven optimisation framework that leverages simulation analysis to identify and selectively reconfigure high-toggle paths. By feeding activity profiles back into a lightweight transformation pass, Simopt-power judiciously inserts duplicate truth table logic using Shannon Decomposition principle and relocates critical nets, thereby attenuating unnecessary transitions without perturbing functional behaviour. We evaluated this framework on open-source RTLLM benchmark, with Simopt-power achieves an average switching-induced power reduction of ~9\\% while incurring only ~9\\% additional LUT-equivalent resources for arithmetic designs. These results demonstrate that coupling simulation insights with targeted optimisations can yield a reduced dynamic power, offering a practical path toward using simulation metadata in the FPGA-CAD flow.","short_abstract":"Excessive switching activity is a primary contributor to dynamic power dissipation in modern FPGAs, where fine-grained configurability amplifies signal toggling and associated capacitance. Conventional low-power techniques -- gating, clock-domain partitioning, and placement-aware netlist rewrites - either require intru...","url_abs":"https://arxiv.org/abs/2510.21745","url_pdf":"https://arxiv.org/pdf/2510.21745v1","authors":"[\"Eashan Wadhwa\",\"Shanker Shreejith\"]","published":"2025-10-07T08:44:33Z","proceeding":"cs.AR","tasks":"[\"cs.AR\",\"cs.DC\"]","methods":"[\"Large Language Model\"]","has_code":false}