{"ID":2852697,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2510.17392","arxiv_id":"2510.17392","title":"ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine","abstract":"We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN approaches, the proposed neuron leverages modular and performance-optimised CORDIC stages with a latency-area trade-off. We introduce a novel Constraint-Aware Modular Parallelism (CAMP) with Precision \u0026 Stability handling to leverage maximum speedup and utilisation of hardware through hardware software co-design. The FPGA implementation of the RCHH neuron shows 24.5% LUT reduction and 35.2% improved speed, compared to SoTA designs, with 70% better normalised root mean square error (NRMSE). Furthermore, the CNP exhibits 2.85x higher throughput (12.69 GOPS) than a functionally equivalent CORDIC-based DNN engine, with only a 0.35% accuracy drop relative to the DNN counterpart on the MNIST dataset. The overall results indicate that the design shows biologically accurate, low-resource spiking neural network implementations for resource-constrained edge AI applications. The reproducibility codes are publicly available at https://github.com/mukullokhande99/CNP RCHH, facilitating rapid integration and further development by researchers.","short_abstract":"We present a Cortical Neural Pool (CNP) architecture featuring a high-speed, resource-efficient CORDIC based Hodgkin-Huxley (RCHH) neuron model. Unlike shared CORDIC-based DNN approaches, the proposed neuron leverages modular and performance-optimised CORDIC stages with a latency-area trade-off. We introduce a novel Co...","url_abs":"https://arxiv.org/abs/2510.17392","url_pdf":"https://arxiv.org/pdf/2510.17392v2","authors":"[\"Sonu Kumar\",\"Arjun S. Nair\",\"Bhawna Chaudhary\",\"Mukul Lokhande\",\"Santosh Kumar Vishvakarma\"]","published":"2025-10-20T10:33:50Z","proceeding":"cs.NE","tasks":"[\"cs.NE\",\"cs.AR\"]","methods":"[]","has_code":false,"code_links":[{"ID":608019,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_id":2852697,"paper_url":"https://arxiv.org/abs/2510.17392","paper_title":"ReLANCE: A Resource-Efficient Low-Latency Cortical Neural Acceleration Engine","repo_url":"https://github.com/mukullokhande99/CNP","is_official":false,"mentioned_in_paper":false,"mentioned_in_github":true,"github_stars":0}]}