{"ID":2851378,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2510.20981","arxiv_id":"2510.20981","title":"FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs","abstract":"Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging. FIFO sizes are user-defined and balance latency and area-undersized FIFOs cause stalls and potential deadlocks, while oversized ones waste memory. Determining optimal sizes is non-trivial: existing methods rely on restrictive assumptions, conservative over-allocation, or slow RTL simulations. We emphasize that runtime-based analyses (i.e., simulation) are the only reliable way to ensure deadlock-free FIFO optimization for data-dependent designs. We present FIFOAdvisor, a framework that automatically determines FIFO sizes in HLS designs. It leverages LightningSim, a 99.9\\% cycle-accurate simulator supporting millisecond-scale incremental runs with new FIFO configurations. FIFO sizing is formulated as a dual-objective black-box optimization problem, and we explore heuristic and search-based methods to characterize the latency-resource trade-off. FIFOAdvisor also integrates with Stream-HLS, a framework for optimizing affine dataflow designs lowered from C++, MLIR, or PyTorch, enabling deeper optimization of FIFOs in these workloads. We evaluate FIFOAdvisor on Stream-HLS design benchmarks spanning linear algebra and deep learning workloads. Our results reveal Pareto-optimal latency-memory frontiers across optimization strategies. Compared to baseline designs, FIFOAdvisor achieves much lower memory usage with minimal delay overhead. Additionally, it delivers significant runtime speedups over traditional HLS/RTL co-simulation, making it practical for rapid design space exploration. We further demonstrate its capability on a complex accelerator with data-dependent control flow. Code and results: https://github.com/sharc-lab/fifo-advisor","short_abstract":"Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging. FIFO sizes are user-defined and balance latency and area-undersized FIFOs cause stalls and potential deadlocks, while oversized ones waste m...","url_abs":"https://arxiv.org/abs/2510.20981","url_pdf":"https://arxiv.org/pdf/2510.20981v1","authors":"[\"Stefan Abi-Karam\",\"Rishov Sarkar\",\"Suhail Basalama\",\"Jason Cong\",\"Callie Hao\"]","published":"2025-10-23T20:17:54Z","proceeding":"cs.AR","tasks":"[\"cs.AR\"]","methods":"[\"LoRA\"]","has_code":false,"code_links":[{"ID":607895,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_id":2851378,"paper_url":"https://arxiv.org/abs/2510.20981","paper_title":"FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs","repo_url":"https://github.com/sharc-lab/fifo-advisor","is_official":false,"mentioned_in_paper":false,"mentioned_in_github":true,"github_stars":0}]}