{"ID":2839629,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2511.15564","arxiv_id":"2511.15564","title":"Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond","abstract":"We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the first open, silicon-proven dual-chiplet RISC-V manycore in 12nm FinFET, we scale to Ramora, a mesh-NoC-based dual-chiplet system, and to Ogopogo, a 7nm quad-chiplet concept architecture achieving state-of-the-art compute density. Finally, we explore possible avenues to extend openness beyond logic-core RTL into simulation, EDA, PDKs, and off-die PHYs.","short_abstract":"We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the first open, silicon-proven dual-chiplet RISC-V manycore in 12nm FinFET, we scale to Ramora, a mesh-NoC...","url_abs":"https://arxiv.org/abs/2511.15564","url_pdf":"https://arxiv.org/pdf/2511.15564v1","authors":"[\"Paul Scheffler\",\"Thomas Benz\",\"Tim Fischer\",\"Lorenzo Leone\",\"Sina Arjmandpour\",\"Luca Benini\"]","published":"2025-11-19T15:58:21Z","proceeding":"cs.AR","tasks":"[\"cs.AR\"]","methods":"[]","has_code":false}