{"ID":2839174,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2511.16557","arxiv_id":"2511.16557","title":"Interfacial and bulk switching MoS2 memristors for an all-2D reservoir computing framework","abstract":"In this study, we design a reservoir computing (RC) network by exploiting short- and long-term memory dynamics in Au/Ti/MoS$_2$/Au memristive devices. The temporal dynamics is engineered by controlling the thickness of the Chemical Vapor Deposited (CVD) MoS$_2$ films. Devices with a monolayer (1L)-MoS$_2$ film exhibit volatile (short-term memory) switching dynamics. We also report non-volatile resistance switching with excellent uniformity and analog behavior in conductance tuning for the multilayer (ML) MoS$_2$ memristive devices. We correlate this performance with trap-assisted space-charge limited conduction (SCLC) mechanism, leading to a bulk-limited resistance switching behavior. Four-bit reservoir states are generated using volatile memristors. The readout layer is implemented with an array of nonvolatile synapses. This small RC network achieves 89.56\\% precision in a spoken-digit recognition task and is also used to analyze a nonlinear time series equation.","short_abstract":"In this study, we design a reservoir computing (RC) network by exploiting short- and long-term memory dynamics in Au/Ti/MoS$_2$/Au memristive devices. The temporal dynamics is engineered by controlling the thickness of the Chemical Vapor Deposited (CVD) MoS$_2$ films. Devices with a monolayer (1L)-MoS$_2$ film exhibit...","url_abs":"https://arxiv.org/abs/2511.16557","url_pdf":"https://arxiv.org/pdf/2511.16557v1","authors":"[\"Asmita S. Thool\",\"Sourodeep Roy\",\"Prahalad Kanti Barman\",\"Kartick Biswas\",\"Pavan Nukala\",\"Abhishek Misra\",\"Saptarshi Das\",\"and Bhaswar Chakrabarti\"]","published":"2025-11-20T17:11:06Z","proceeding":"cs.ET","tasks":"[\"cs.ET\",\"cs.AI\"]","methods":"[]","has_code":false}