{"ID":2831722,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2512.07602","arxiv_id":"2512.07602","title":"Algorithm-hardware co-design of neuromorphic networks with dual memory pathways","abstract":"Spiking neural networks excel at event-driven sensing. Yet, maintaining task-relevant context over long timescales both algorithmically and in hardware, while respecting both tight energy and memory budgets, remains a core challenge in the field. We address this challenge through an algorithm-hardware co-design effort. At the algorithm level, inspired by the cortical fast-slow organization in the brain, we introduce a neural network with an explicit slow memory pathway that, combined with fast spiking activity, enables a dual memory pathway (DMP) architecture in which each layer maintains a compact low-dimensional state that summarizes recent activity and modulates spiking dynamics. This explicit memory stabilizes learning while preserving event-driven sparsity, achieving competitive accuracy on long-sequence benchmarks with 40-60% fewer parameters than equivalent state-of-the-art spiking neural networks. At the hardware level, we introduce a near-memory-compute architecture that fully leverages the advantages of the DMP architecture by retaining its compact shared state while optimizing dataflow, across heterogeneous sparse-spike and dense-memory pathways. We show experimental results that demonstrate more than a 4X increase in throughput and over a 5X improvement in energy efficiency compared with state-of-the-art implementations. Together, these contributions demonstrate that biological principles can guide functional abstractions that are both algorithmically effective and hardware-efficient, establishing a scalable co-design framework for real-time neuromorphic computation and learning.","short_abstract":"Spiking neural networks excel at event-driven sensing. Yet, maintaining task-relevant context over long timescales both algorithmically and in hardware, while respecting both tight energy and memory budgets, remains a core challenge in the field. We address this challenge through an algorithm-hardware co-design effort....","url_abs":"https://arxiv.org/abs/2512.07602","url_pdf":"https://arxiv.org/pdf/2512.07602v3","authors":"[\"Pengfei Sun\",\"Zhe Su\",\"Jascha Achterberg\",\"Giacomo Indiveri\",\"Dan F. M. Goodman\",\"Danyal Akarca\"]","published":"2025-12-08T14:50:26Z","proceeding":"cs.NE","tasks":"[\"cs.NE\"]","methods":"[\"Generative Adversarial Network\"]","has_code":false}