{"ID":2829139,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2512.13686","arxiv_id":"2512.13686","title":"Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing","abstract":"As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to $1.27\\times$ higher coverage and accelerates end-to-end verification by up to $107\\times$ to $3343\\times$ compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.","short_abstract":"As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to...","url_abs":"https://arxiv.org/abs/2512.13686","url_pdf":"https://arxiv.org/pdf/2512.13686v3","authors":"[\"Juncheng Huo\",\"Yunfan Gao\",\"Xinxin Liu\",\"Sa Wang\",\"Yungang Bao\",\"Xitong Gao\",\"Kan Shi\"]","published":"2025-12-15T18:59:53Z","proceeding":"cs.AR","tasks":"[\"cs.AR\"]","methods":"[]","has_code":false}