{"ID":2828629,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2512.14642","arxiv_id":"2512.14642","title":"An Energy-Efficient Adiabatic Capacitive Neural Network Chip","abstract":"Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under stringent energy constraints, especially for battery-powered and edge devices. To address this, we present a mixed-signal adiabatic capacitive neural network chip, designed in a 130$nm$ CMOS technology, to demonstrate significant energy savings coupled with high image classification accuracy. Our dual-layer hardware chip, incorporating 16 single-cycle multiply-accumulate engines, can reliably distinguish between 4 classes of 8x8 1-bit images, with classification results over 95\\%, within 2.7\\% of an equivalent software version. Energy measurements reveal average energy savings between 2.1x and 6.8x, compared to an equivalent CMOS capacitive implementation.","short_abstract":"Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under stringent energy constraints, especially for battery-powered and edge devices. To...","url_abs":"https://arxiv.org/abs/2512.14642","url_pdf":"https://arxiv.org/pdf/2512.14642v2","authors":"[\"Himadri Singh Raghav\",\"Sachin Maheshwari\",\"Mike Smart\",\"Patrick Foster\",\"Alex Serb\"]","published":"2025-12-16T17:59:40Z","proceeding":"eess.IV","tasks":"[\"eess.IV\"]","methods":"[]","has_code":false}