{"ID":2827952,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2512.15251","arxiv_id":"2512.15251","title":"Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators","abstract":"Fully parallel neural network accelerators on field-programmable gate arrays (FPGAs) offer high throughput for latency-critical applications but face hardware resource constraints. Weightless neural networks (WNNs) efficiently replace arithmetic with logic-based inference. Differential weightless neural networks (DWN) further optimize resource usage by learning connections between encoders and LUT layers via gradient-based training. However, DWNs rely on thermometer encoding, and the associated hardware cost has not been fully evaluated. We present a DWN hardware generator that includes thermometer encoding explicitly. Experiments on the Jet Substructure Classification (JSC) task show that encoding can increase LUT usage by up to 3.20$\\times$, dominating costs in small networks and highlighting the need for encoding-aware hardware design in DWN accelerators.","short_abstract":"Fully parallel neural network accelerators on field-programmable gate arrays (FPGAs) offer high throughput for latency-critical applications but face hardware resource constraints. Weightless neural networks (WNNs) efficiently replace arithmetic with logic-based inference. Differential weightless neural networks (DWN)...","url_abs":"https://arxiv.org/abs/2512.15251","url_pdf":"https://arxiv.org/pdf/2512.15251v1","authors":"[\"Michael Mecik\",\"Martin Kumm\"]","published":"2025-12-17T09:49:43Z","proceeding":"cs.AR","tasks":"[\"cs.AR\"]","methods":"[]","has_code":false}