{"ID":2825778,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2512.21362","arxiv_id":"2512.21362","title":"Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide","abstract":"Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This work represents that this design's Correlation Power Analysis (CPA) reveals significant leakage, enabling key recovery. These findings underscore the importance of early-stage RTL assessments in shaping future secure RISC-V designs.","short_abstract":"Security in modern RISC-V processors demands more than functional correctness: It requires resilience to side-channel attacks. This paper evaluates the vulnerability of the side channel of the CVA6 RISC-V core by analyzing software-based AES encryption uses an RTL-level power profiling framework called VeriSide. This w...","url_abs":"https://arxiv.org/abs/2512.21362","url_pdf":"https://arxiv.org/pdf/2512.21362v1","authors":"[\"Behnam Farnaghinejad\",\"Antonio Porsia\",\"Annachiara Ruospo\",\"Alessandro Savino\",\"Stefano Di Carlo\",\"Ernesto Sanchez\"]","published":"2025-12-23T10:41:27Z","proceeding":"cs.CR","tasks":"[\"cs.CR\",\"cs.AR\"]","methods":"[]","has_code":false}