{"ID":2824872,"CreatedAt":"2026-06-01T04:54:23.091178241Z","UpdatedAt":"2026-06-01T04:54:23.091178241Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2512.22676","arxiv_id":"2512.22676","title":"Synthesis of signal processing algorithms with constraints on minimal parallelism and memory space","abstract":"This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a power/energy consumption model for clocked CMOS logic that supports selecting optimal parallelism, (ii) integer-friendly approximation methods for elementary functions that reduce lookup-table size via constrained piecewise-polynomial (quasi-spline) constructions with accuracy guarantees, (iii) provably conflict-free data placement and execution order for mixed-radix streaming FFT on multi-bank and single-port memories, including a self-sorting FFT variant, and (iv) a parallelism/memory analysis of the fast Schur algorithm for superfast Toeplitz system solving, motivated by echo-cancellation workloads. The results provide constructive theorems, schedules, and design trade-offs enabling efficient specialized accelerators.","short_abstract":"This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a power/energy consumption model for clocked CMOS logic that supports selecting optimal par...","url_abs":"https://arxiv.org/abs/2512.22676","url_pdf":"https://arxiv.org/pdf/2512.22676v1","authors":"[\"Sergey Salishev\"]","published":"2025-12-27T18:48:14Z","proceeding":"eess.SP","tasks":"[\"eess.SP\",\"cs.AR\",\"cs.DC\",\"math.NA\"]","methods":"[]","has_code":false}