{"ID":23475182,"CreatedAt":"2026-09-18T01:09:05.407443952Z","UpdatedAt":"2026-09-20T18:11:56.143995915Z","DeletedAt":null,"paper_url":"https://arxiv.org/abs/2609.19999","arxiv_id":"2609.19999","title":"Evaluating Positive Feedback Adiabatic Logic in 16nm FinFET with a Realistic Power-Clock","abstract":"Adiabatic logic reuses the energy stored on load capacitances through quasi-reversible switching, enabling a lower minimum energy consumption than conventional static CMOS. Yet its practicality in FinFET technologies and at multi-GHz clock rates has yet to be investigated. This work provides a systematic evaluation of Positive Feedback Adiabatic Logic (PFAL) simulated in the TSMC 16nm FinFET process. A set of PFAL standard-cell gates were realised, along with two representative combinational circuits - a 2$\\times$2 multiplier and a 4-bit comparator - and compared against static CMOS logic using the energy--delay product (EDP) and the energy advantage metric $η= E_{\\mathrm{CMOS}} / E_{\\mathrm{PFAL}}$. Transient simulations reveal three sources of non-adiabatic loss: two specific to the PMOS/NMOS latch, threshold-voltage-related loss and a previously unreported redundant charging of the output node and one related to the complexity of PFAL logic trees. The low-threshold Buffer/NOT cell achieves a minimum EDP of $1.23\\times10^{-26}$J$\\cdot$s at $V_{\\mathrm{CLK}} = 0.6$V and $f_{\\mathrm{CLK}} = 7.94$GHz, while PFAL preserves an energy benefit over static CMOS of up to roughly $5\\times$ at reduced frequencies and elevated supply voltages. A parallel-coupled quadrature voltage-controlled oscillator is designed as a realistic four-phase power-clock generator. With this non-ideal supply, the Buffer/NOT energy stays within $2\\%$ of the ideal sinusoidal case at $3$GHz. A loading study quantifies the phase shift and amplitude reduction induced by increasing fan-out. Overall, the results provide a design-oriented evaluation of PFAL in 16nm FinFET and a motivation to exploit adiabatic logic for future low-power system architectures.","short_abstract":"Adiabatic logic reuses the energy stored on load capacitances through quasi-reversible switching, enabling a lower minimum energy consumption than conventional static CMOS. Yet its practicality in FinFET technologies and at multi-GHz clock rates has yet to be investigated. This work provides a systematic evaluation of...","url_abs":"https://arxiv.org/abs/2609.19999","url_pdf":"https://arxiv.org/pdf/2609.19999v1","authors":"[\"Franciszek Łukowski\",\"Maciej Pyrzowski\",\"Aida Todri-Sanial\"]","published":"2026-09-17T10:06:46Z","proceeding":"cs.AR","tasks":"[\"cs.AR\"]","methods":"[]","has_code":false}